趁着比特币疯长再发一波 AI 部门的招聘

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比特大陆精益求精，用芯制造。现在三岁了，家人们都十分重视每一位伙伴的加入，每一滴新鲜的血液，都会很大程度上影响着公司的文化和发展，所以我们对此十分谨慎，也非常挑剔，直到遇见适合 [比特大陆] 企业文化的你。 —— 比特大陆 CEO 詹克团比特大陆 AI 产品线开始招聘啦！～我们开放芯片研发、软件、算法、硬件、市场、文案等众多岗位职位要求相对较高，但是薪水绝对给力。感兴趣的可以将简历发送到：[email protected] ，直接内推到负责人。有任何公司方面的问题，欢迎大家邮件咨询，也可以交换微信号私下交流。

开放职位

IC 类（北京 /武汉 /成都 /深圳）

资深芯片设计工程师 
资深全定制芯片设计工程师 
资深 FPGA 设计工程师 
资深芯片验证工程师 
资深芯片后端设计工程师 
资深 DFT 工程师 
集成电路相关专业的实习生 若干 


软件类 （北京 /武汉 /成都 /深圳）

资深芯片嵌入式软件工程师
系统软件开发工程师 
应用软件开发工程师 
资深计算机系统结构工程师 
资深编译器工具链工程师 
高性能计算工程师 
计算机软件相关的实习生 若干 


算法类 （北京 /武汉 /成都 /深圳）

深度学习研发工程师 北京武汉成都深圳 
计算机视觉研发工程师 
机器学习算法工程师 
AI、ML、模式识别、数学相关的实习生 若干 


硬件类 （北京 /武汉 /成都 /深圳）

资深硬件工程师 /硬件技术专家 


市场文案类 （北京）

全职、兼职、实习生

Part 1

▬ 关于 BITMAIN ▬

▌我们是谁

[北京比特大陆科技有限公司] 是一家专注于高速、低功耗定制芯片设计研发的纯科技公司，拥有最性感的 16nm 工艺集成电路全定制设计的量产经验，成功开发并量产了多款 ASIC 定制芯片和整机系统。

公司大本营位于北京，在美国旧金山、以色列特拉维夫、荷兰阿姆斯特丹均设有研发中心，并在成都、青岛、深圳、武汉等设有分公司。

▌我们想要做什么

比特大陆落脚于每一个技术性能的革新和算法的迭代，站在科技前沿的肩膀上，守护每一颗智能芯片的速率。

早在 2014 年底，比特大陆敏锐的捕捉到了人工智能的新趋势，借助集成电路设计量产的优势，带领团队投身深度学习芯片加速板卡及服务器，并进一步扩展云基础设施到人工智能计算领域，我们的目标是让大数据用户借助我们的云平台更快速的开发和部署他们的深度学习应用。

尽管现在我们还不是人工智能的巨头，既不是扩张速度最快的，也不是最善推广的，但我们对专业的坚守、对行业的理解，终将使我们成为征途中最耀眼的那一个。

▌比特大陆提供什么样的产品服务

致力于研发时代潮流所趋、又独具魅力及无限未来空间的 [人工智能芯片及硬件产品] 。将秉承我们一贯的气质，在这场“贵族游戏”（世界 AI 芯）中继续精益求精、极致卓越！！！

▌我们的小骄傲

推出我国第一款 55nm 制程的 SHA256 运算的加速芯片—— BM1380，为数字货币交易认证提供了高安全的服务系统。

比特大陆陆续突破了 28nm 工艺、16nm 的工艺制程，其中 BM1387 芯片的单片计算速度高达 80GH/S，在 0.4V 的核心电压下功耗仅为 0.079W/GH/s，该芯片量产的服务系统综合性能高达 12.9TH/S，功耗仅为 1200W，我们运营了 100 兆瓦电力的全球服务器基础设施，产出约 300Petahash/s 算力。

▌你未来的伙伴

现有 500+名优秀的小伙伴已加入比特大陆大家庭，70%以上从事的是芯片与系统的研发工作。这里不仅有 AI 届的神秘大拿坐镇，陪伴你的还有清华少年班的硕士正太，耶鲁海龟的高级攻城狮、还有来自北大、中科院、港大等顶级技术极客、商务牛人，当然还有一群有爱的小伙伴，陪你成长，陪你快乐！

Part 2 ▬ 你将得到什么 ▬

丰厚薪金福利+项目奖金+年度奖金六险一金+节日福利+带薪年假食堂+班车+弹性工作时间每年一次免费体检+集体出游+员工生日会+下午茶歇良好的办公环境(独栋写字楼、休闲设施、健身中心)

Part 3 ▬ 详细岗位描述和应聘需求 ▬

—— 软件类 ——

▌资深芯片嵌入式软件工程师 Senior Embedded Software Engineer

Responsibilities:

Design, implement, validateand debug through firmware, device drivers, framework software, and applicationsoftware
Make changes to Linux kerneland write kernel/user space drivers/applications as and when required
Bring up of x86 based serveras well as bare metal SoC system
Analyze and tune for optimalperformance and efficiency
Develop relevant tools orscripts
Participate in all phases ofa product development

Requirements:

MSCS/MSEE with 2+ years orBSCS/BSEE with 5 years of relevant experience
Excellent C/C++/Assemblydevelopment and debugging skills
Detailed and extensiveexperience with Linux kernel software is required
Strong understanding of CPUarchitecture, bus, PCIe, and peripheral interfaces
Experience in EmbeddedOS/RTOSes preferred
Experience with GPU or othercompute/data-intensive device driver development preferred
Passionate about solvingfundamental problems
Good team player

▌系统软件开发工程师 Senior System Software Engineer

Responsibilities:

Design, implement, validateand debug through firmware, device drivers, framework software, and applicationsoftware
Deliver and maintain SDKand APIs for the architecture design, integrate with platform and applicationsoftware
Understand and analyzehardware features, leading to recommendations for future architectures
Analyze performance andtune for optimal performance and efficiency
Develop relevant tools orscripts
Participate in all phases ofa product development

Requirements:

MSCS/MSEE with 2+ years ofrelevant experience or PhD preferred
Excellent C/C++/Pythondevelopment and debugging skills
Solid background inmathematics, algorithms and data structures
Experience working with oneof the following areas: CUDA, 3D graphics, OpenCL, DSP, Neon, SSE, AVX, FMA, orother parallel processing systems
Good understanding ofconcepts related to computer architecture and operating systems
Passionate about solvingfundamental problems
Experience in machinelearning is a plus
Good team player

▌资深计算机系统结构工程师 Senior Computer Architecture Engineer

Responsibilities:

MS or PHD Degree inrelevant discipline (CS, EE, Math)
Strong programming skillsin C or C++
Strong background incomputer architecture, parallel processing, signal processing and/or highperformance computing

Ways To Stand Out From The Crowd

Big plus wit deep learning,computer vision and HPC domain
Experience incharacterizing and modeling system-level performance or power, executingcomparison studies, and documenting and publishing results

▌高性能计算工程师

工作职责:

在可编程的专用芯片上(类似于 google 最近推出的 TPU)上开发 firmware，充分使用芯片上的硬件资源来完成机器学习任务

任职资格:

有针对高复杂度算法的优化经验(比如机器学习算法 /图像处理算法 /视频编解码算法 /基带信号处理等领域) 以下两个背景中最少要有一项
使用过 GPU 或是汇编语言做软件优化
芯片设计背景
了解计算机体系结构的基本原理.对软硬件协同工作有一定认识
有深度学习背景者加分。
欢迎有芯片设计经验又愿意转行做软件的人
职位关键字:并行计算 /芯片 / 计算机体系结构 / GPU/ CUDA / OpenCL / 汇编优化 / SSE / NEON

—— 算法类 ——

▌深度学习研发工程师 Deep Learning Engineer

工作职责:

从事前沿人工智能技术研发
至少涉及以下一种职责，计算机视觉，自然语言处理，深度学习平台，语音识别的研发

任职资格:

熟练掌握 C/C++，Python
有一定的深度学习基础，能熟练使用 Caffe，Torch，TensorFlow 等深度学习平台中的任意一个优先
在以下至少一个领域有深入的研究：大规模机器学习、自然语言处理、计算机视觉、图像处理，语音识别
有宽泛的技术视野和对人工智能的热情
在计算机视觉国际顶级会议或者期刊上发表论文、国际比赛获奖、及有相关专利者优先

▌计算机视觉研发工程师 Computer Vision Engineer

工作职责:

负责公司计算机视觉相关的技术、系统、产品的研发工作(人脸检测识别、图像分类标注、OCR、图像处理等)
负责公司计算机视觉方向技术难点攻关、前瞻研究以及初级工程师的指导

任职资格:

熟练掌握 C/C++，Python
熟练掌握机器学习基本算法并有一定的实践经验
有一定的深度学习基础，能熟练使用 Caffe，Torch，TensorFlow 等深度学习平台中的任意一个优先
熟练掌握计算机视觉和图像处理基本算法并具有丰富的相关经验（人脸检测识别、图像分类标注、OCR 等）
有宽泛的技术视野和对人工智能的热情
在计算机视觉国际顶级会议或者期刊上发表论文、国际比赛获奖、及有相关专利者优先

▌机器学习算法工程师 Machine Learning Engineer

Responsibilities:

Development andimplementation of DL/ML algorithms focusing on industrial applications, suchas, driver-less cars, robotics, internet of things, and industry 4.0
Strategy development forthe field of AI/DL/ML, support in strategic decision making with regard to ourvarious product lines
Development of large scaleDL/ML algorithms and parallel implementation strategies
Evaluation and comparisonof DL/ML algorithms for specific applications and related tasks, in particularwith regard to the performance, training, and suitability for embeddedapplications
Close communication withour hardware architecture experts

Requirements:

PhD in computer science,artificial intelligence, mathematics, physics, statistics
Expertise and practicalexperience in the following domains: Artificial Intelligence, Deep Learning,Machine Learning. Practical experience in CNN/NLP algorithm is a plus
Indepth practice in deeplearning methodologies on GPU/FPGA/ASIC, such as Caffe, ConvNet, Torch … etc.,mastering the tuning strategy for CNN/NLP's parameters Technical proficiency inprogramming languages: R, C/C++, Python, Matlab, Java, JavaScript, familiaritywith Linux environment
Experience with big datatechnologies and HPC is a plus, such as Hadoop ecosystem
Excellent communicativeskills in read and written English, fluent spoken English
Strong communicationskills, ability to express oneself logically, strong sense of team spirit,proactive communication

—— IC 类 ——

▌资深芯片设计工程师 Senior IC/ASIC/SOC Design Expert

Responsibilities:

IC Block design for all frontend phase
IC chip level design for all font-end phase
Architecture define
RTL implementation
Analysis and Optimization for performance
Analysis and Optimization for power
Analysis and Optimization for timing
Design flow: lint/synthesis/sta/formal check
Silicon debugging

Requirements:

BS / MS with 5+ years of experience in ASIC or FPGA design
Experience with CPU related IPs design are highly desirable
Experience as design lead for complex or high speed IPs
Experience with all phases of frontend architecture, design and validation
RTL Coding, Design Reviews, SYN, CDC, FEV, DFT insertion, ATPG analysis
Demonstrated work experience with timing Analysis, Area and Power optimizations, * Performance Analysis, Debug ability and Security analysis, ECOs, and Post-Silicon Debug
Excellent knowledge of Verilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages

▌资深全定制芯片设计工程师 Senior Full Custom IC Design Expert

Responsibilities:

Architecture design for custom chip
Function block front end design for custom chip
Full chip design for custom ASIC

Requirements:

BS / MS with 5+ years of experience in IC design
Solid theory understanding for digital and analog circuitry
Experience with circuit level customization, for example: SRAM / Adders / Mux etc
Experience with non-standard-cell based IC design is a plus
Experience with library characterization is a plus
Excellent knowledge of Verilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages

▌资深 FPGA 设计工程师 Senior FPGA Design Engineer

Responsibilities:

FPGA prototype implementation for complicated SOC system
Setup FPGA simulation env for fuction verification
FPGA Board bring up and debug

Requirements:

Master degree or above, 5+ years or more working experience
Strong Verilog RTL coding, and testbench design skills; Good understanding of digital circuits
Good Understanding of synthesis, simulation, P&R flow, timing analysis and relevant tools for FPGA and ASIC
Familiar with design tools of Xilinx, Altera
Familiar with SOC system design
Rich board debug experience

▌资深芯片验证工程师 Senior IC Verification Engineer

Responsibilities:

Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
Create verification environment for both directed and random verification
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage driven verification closure
Work with architects, designers and post-silicon teams

Requirements:

BS / MS with 5+ years of experience in design verification
Experience in design verification for CPU related IPs are highly desirable
Experience as verification lead for complex IP
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Simvision)
Expertise in Verilog
Excellent communication skills and ability to lead highly competent team.
Experience in SystemVerilog or similar HVL is highly desirable
Strong debugging and problem solving skills
Scripting knowledge (Perl/shell)
Strong fundamentals in computer architecture desirable
C++ programming language experience desirable

▌资深芯片后端设计工程师 Senior ASIC Backend DesignEngineer

Responsibilities:

Execute the whole Physical Design flow includeFloorplan/Placement/CTS/Routing/Physical Verification
Work with front end design Engineers to achieve timingclosure for both partition level and full chip level
IO ring design
Cross talk Analysis
IR Drop and Power Integrity Analysis
Execute ECO's
Develop and enhance entire physical design flow at bothchip and block level

Requirements:

BS/MS in Electrical or Computer Engineering with 5+ yearsexperience in physical design
Experience with advanced process, experience with hierarchicaldesign flow
Hands-on experience in full-chip/sub-chip Static TimingAnalysis. CPU related timing convergence background would be a plus
Hands on experience in logic synthesis and equivalencechecking/FV required
Expertise in physical design and optimization e.g.placement, routing, cell sizing, buffering, logic restructuring, etc. toimprove timing and power required. * Background in implementing them through ECOsrequired
Understanding of DFT logic and hands-on experience in designclosure taking into account DFT logic required. DFT timing closure for variousmodes e.g. scan shift and capture, transition faults, BIST, etc. would be aplus
Expertise in analyzing and converging crosstalk delay,noise glitch, and electrical/manufacturing rules in deep-sub micron processes
Understand process variation effect modeling andexperience in design convergence taking into account variations required
Experience in critical path planning and crafting.Experience in circuits, SPICE simulations, and/or transistor level STA would bea plus
Expertise and in-depth knowledge of industry standard EDAtools required Proficiency in scripting languages, such as, Perl, Tcl,Make, etc. Experience in methodology and/or flow automation would be a plus

—— 硬件类 ——

▌资深硬件工程师 /硬件技术专家 Senior Hardware Engineer/Expert

Responsibilities:

Designing, simulating,prototyping, and testing of electrical systems Parts selection andqualification
Transform vendor referencedesigns into custom solutions
Build schematic, boardfloor planning, pre-layout planning based on simulations Provide guidance to CADdesigners (placement and routing) and review CAD work Lead and participate informal design reviews
Author HW specifications,and publish bill of materials
Bring up and testprototypes
Develop and Implement testplans
Lab debug of HW problems

Requirements：

5+ years of experience indigital/analog electrical system design
Proficient in the completeflow of CAD design tools
Proficient in constraintdriven design methodologies
Proficient in usingoscilloscopes, high speed digital test equipment, logic analyzers, and functiongenerators
Experience with the use ofhigh performance processors and support FPGAs
Strong knowledge and applicationof high-speed design methodologies for Signal Integrity is a must
Experience with effectivePCB stack-up design is a must
Experience with high speedbuses include: PCIe QPI, Multi-gigabit Ethernet, Infiniband, DDR3/DDR4
FPGA design experience is aplus
Experience with digital oranalog simulation is a plus
Digital signal processing,real-time image processing, and camera module experience is a plus
Strong communication skills